The parallel-to-serial converter circuit according to claim 1, when parallel signals including fifth to twelfth input data signals, respectively having data changing at a second given cycle that is twice the given cycle, are converted into a serial signal, the parallel-to-serial converter circuit further comprising: a fourth multiplexer that at each second given cycle, outputs the sixth input data signal, after outputting the fifth input data signal a fifth multiplexer that at each second given cycle, outputs the eighth input data signal, after outputting the seventh input data signal a sixth multiplexer that at each second given cycle, outputs a tenth input data signal, after outputting a ninth input data signal and a seventh multiplexer that at each second given cycle, outputs the twelfth input data signal, after outputting the eleventh input data signal, wherein the first multiplexer switches at half cycles of the given cycle, output of a signal that is from the fourth multiplexer and output of a signal that is from the fifth multiplexer, and the second multiplexer switches at half cycles of the given cycle, output of a signal that is from the sixth multiplexer and output of a signal that is from the seventh multiplexer. The parallel-to-serial converter circuit according to claim 1, wherein the second clock signal is a signal having a phase that differs from the phase of the first clock signal by 90 degrees.ĥ. The parallel-to-serial converter circuit according to claim 1, wherein the first multiplexer, at each half cycle of the given cycle and according to the second clock signal that is of the given cycle and has a phase differing from the phase of the first clock signal, alternates output of the first input data signal that is from the first latch group and output of the second input data signal that is from the second latch group, the second multiplexer, at each half cycle of the given cycle and according to the second clock signal, alternates output of the third input data signal that is from the third latch group and output of the fourth input data signal that is from the fourth latch group, and the third multiplexer, at each half cycle of the given cycle and according to the first clock signal, alternates output of a signal that is from the first multiplexer and output of a signal that is from the second multiplexer.Ĥ.
The parallel-to-serial converter circuit according to claim 1, wherein the first multiplexer switches at half cycles of the given cycle, output of the first input data signal and output of the second input data signal, the second multiplexer switches at half cycles of the given cycle, output of the third input data signal and output the fourth input data signal, and the third multiplexer switches at half cycles of the given cycle, output of a signal that is from the first multiplexer and output of a signal that is from the second multiplexer.ģ.
A parallel-to-serial converter circuit that converts parallel first to fourth input data signals into a serial signal, the parallel-to-serial converter circuit comprising: a first latch group that based on a first clock signal of a given cycle, outputs the first input data signal at a first timing of the given cycle a second latch group that outputs the second input data signal at a second timing that is of the given cycle and delayed by half a cycle of the given cycle relative to the first timing a third latch group that outputs the third input data signal at the second timing a fourth latch group that outputs the fourth input data signal at a third timing that is of the given cycle and delayed by one given cycle relative to the first timing a first multiplexer that at each given cycle and based on a second clock signal having a phase that differs by ¼ cycle from the phase of the first clock signal, outputs the second input data signal, after outputting the first input data signal a second multiplexer that at each given cycle and based on the second clock signal, outputs the fourth input data signal, after outputting the third input data signal and that outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer and a third multiplexer that at each given cycle and based on the first clock signal, outputs the third and the fourth input data signals output from the second multiplexer, after outputting the first and the second input data signals output front the first multiplexer.Ģ.